Altera cyclone V Technical Reference page 2058

cv_5v4
2016.10.28
Transmit_Descriptor_List_Address Fields
Bit
31:2
tdesla_32bit
Status
The Status register contains all status bits that the DMA reports to the host. The software driver reads this
register during an interrupt service routine or polling. Most of the fields in this register cause the host to
be interrupted. The bits of this register are not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0]
of this register clears these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by
masking the appropriate bit in Register 7 (Interrupt Enable Register).
Module Instance
emac0
emac1
Offset:
0x1014
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved glpii tti
RO
0x0 0x0
15 14
ais eri fbi
RW 0x0 RW
0x0 0x0
Ethernet Media Access Controller
Send Feedback
Name
This field contains the base address of the first
descriptor in the Transmit Descriptor list. The LSB
bits (1:0) are ignored (32-bit wide bus) and are
internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only (RO).
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reser gmi gli
ved
RO RO RO
0x0 0x0
13 12 11 10
Reserved eti
RW RW
0x0
Description
Base Address
Bit Fields
25 24 23 22
eb
RO 0x0
9 8 7 6
rwt rps ru ri
RW RW RW RW
0x0 0x0 0x0 0x0
Register Address
0xFF701014
0xFF703014
21 20 19 18
ts rs
RO 0x0 RO 0x0
5 4 3 2
unf ovf tjt tu
RW RW RW RW
0x0 0x0 0x0 0x0
17-843
Status
Access Reset
RW 0x0
17 16
nis
RW 0x0
1 0
tps ti
RW RW 0x0
0x0
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