Altera cyclone V Technical Reference page 2070

cv_5v4
2016.10.28
Bit
1
sr
Interrupt_Enable
The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to
1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Module Instance
emac0
emac1
Offset:
0x101C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Ethernet Media Access Controller
Send Feedback
Name
When this bit is set, the Receive process is placed in
the Running state. The DMA attempts to acquire the
descriptor from the Receive list and processes the
incoming frames. The descriptor acquisition is
attempted from the current position in the list, which
is the address set by Register 3 (Receive Descriptor
List Address Register) or the position retained when
the Receive process was previously stopped. If the
DMA does not own the descriptor, reception is
suspended and Bit 7 (Receive Buffer Unavailable) of
Register 5 (Status Register) is set. The Start Receive
command is effective only when the reception has
stopped. If the command is issued before setting
Register 3 (Receive Descriptor List Address Register),
the DMA behavior is unpredictable. When this bit is
cleared, the Rx DMA operation is stopped after the
transfer of the current frame. The next descriptor
position in the Receive list is saved and becomes the
current position after the Receive process is restarted.
The Stop Receive command is effective only when the
Receive process is in either the Running (waiting for
receive packet) or in the Suspended state.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Rx DMA operation is stopped
Rx DMA operation is started
Base Address
0xFF70101C
0xFF70301C
17-855
Interrupt_Enable
Access Reset
RW 0x0
Register Address
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