Altera cyclone V Technical Reference page 2051

17-836
Bus_Mode
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
Reserved
Bus_Mode Fields
Bit
25
aal
24
eightxpbl
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
pbl
RW 0x1
Name
When this bit is set high and the FB bit is equal to 1,
the AHB or AXI interface generates all bursts aligned
to the start address LS bits. If the FB bit is equal to 0,
the first burst (accessing the data buffer's start
address) is not aligned, but subsequent bursts are
aligned to the address.
Value
0x0
0x1
When set high, this bit multiplies the programmed
PBL value (Bits[22:17] and Bits[13:8]) eight times.
Therefore, the DMA transfers the data in 8, 16, 32, 64,
128, and 256 beats depending on the PBL value.
Value
0x0
0x1
Bit Fields
25 24 23 22
aal eight usp
xpbl
RW RW
0x0 RW 0x0
0x0
9 8 7 6
atds
RW
0x0
Description
Description
No Address-Aligned Beats
Address-Aligned Beats (dependent on FB)
Description
Non Multiply Mode
Multiplies PBL value by 8
21 20 19 18
rpbl
RW 0x1
5 4 3 2
dsl
RW 0x0
Access
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
fb
RW 0x0
1 0
Reser swr
ved
RW 0x1
Reset
RW 0x0
RW 0x0
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