Altera cyclone V Technical Reference page 2069

Hard processor system
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17-854
Operation_Mode
Bit
6
fuf
4:3
rtc
2
osf
Altera Corporation
Name
When set, the Rx FIFO forwards Undersized frames
(frames with no Error and length less than 64 bytes)
including pad-bytes and CRC. When reset, the Rx
FIFO drops all frames of less than 64 bytes, unless a
frame is already transferred because of the lower
value of Receive Threshold, for example, RTC = 01.
Value
0x0
0x1
These two bits control the threshold level of the MTL
Receive FIFO. Transfer (request) to DMA starts when
the frame size within the MTL Receive FIFO is larger
than the threshold. In addition, full frames with
length less than the threshold are transferred
automatically. These bits are valid only when the RSF
bit is zero, and are ignored when the RSF bit is set to
1.
Value
0x0
0x1
0x2
0x3
When this bit is set, it instructs the DMA to process
the second frame of the Transmit data even before the
status for the first frame is obtained.
Value
0x0
0x1
Description
Description
Drops Frames less than 64Bytes
Forward Frames with no errors
Description
MTL Rcv Fifo threshold level 64
MTL Rcv Fifo threshold level 32
MTL Rcv Fifo threshold level 96
MTL Rcv Fifo threshold level 128
Description
DMA Does Not Process second frame
DMA Processes second frame
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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