Altera cyclone V Technical Reference page 2057

17-842
Transmit_Descriptor_List_Address
Receive_Descriptor_List_Address Fields
Bit
31:2
rdesla_32bit
Transmit_Descriptor_List_Address
The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The
descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned
(for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by
making the corresponding LSB to low. You can write to this register only when the Tx DMA has stopped,
that is, Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can
be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly
programmed descriptor base address. If this register is not changed when the ST bit is set to 0, then the
DMA takes the descriptor address where it was stopped earlier.
Module Instance
emac0
emac1
Offset:
0x1010
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Altera Corporation
Name
This field contains the base address of the first
descriptor in the Receive Descriptor list. The LSB bits
(1:0) are ignored (32-bit wide bus) and internally
taken as all-zero by the DMA. Therefore, these LSB
bits are read-only (RO).
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
tdesla_32bit
Description
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
tdesla_32bit
RW 0x0
9 8 7 6
RW 0x0
Access
Register Address
0xFF701010
0xFF703010
21 20 19 18
5 4 3 2
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RW 0x0
17 16
1 0
Reserved
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