Altera cyclone V Technical Reference page 2068

Hard processor system

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Ethernet Media Access Controller

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These bits control the threshold (Fill level of Rx FIFO)

at which the flow control is activated. These values

only apply to the Rx FIFO when the EFC bit is set

When this bit is set, the flow control signal operation

based on the fill-level of Rx FIFO is enabled. When

reset, the flow control operation is disabled.

When this bit is reset, the Rx FIFO drops frames with

error status (CRC error, collision error, GMII_ER,

giant frame, watchdog timeout, or overflow).

However, if the start byte (write) pointer of a frame is

already transferred to the read controller side (in

Threshold mode), then the frame is not dropped.

When the FEF bit is set, all frames except runt error

frames are forwarded to the DMA. If the Bit 25 (RSF)

is set and the Rx FIFO overflows when a partial frame

is written, then the frame is dropped irrespective of

the FEF bit setting. However, if the Bit 25 (RSF) is

reset and the Rx FIFO overflows when a partial frame

is written, then a partial frame may be forwarded to

Full minus 1 KB

Full minus 2 KB

Full minus 3 KB

Full minus 4 KB

Rx FIFO Fill Level Disabled

Rx FIFO Fill Level Enabled Ctrl

Drops Frames with error status

Forward all Frames(except runt)

Operation_Mode

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