Altera cyclone V Technical Reference page 2060

cv_5v4
2016.10.28
Bit
26
gli
25:23
eb
22:20
ts
Ethernet Media Access Controller
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Name
This bit reflects an interrupt event in the PCS (link
change and AN complete), SMII (link change), or
RGMII (link change) interface block of the EMAC.
The software must read the corresponding registers
(Register 49 for PCS or Register 54 for SMII or
RGMII) in the EMAC to get the exact cause of the
interrupt and clear the source of interrupt to make
this bit as 1'b0. The interrupt signal from the EMAC
subsystem (sbd_intr_o) is high when this bit is high.
Value
0x0
0x1
This field indicates the type of error that caused a Bus
Error, for example, error response on the AHB or AXI
interface. This field is valid only when Bit 13 (FBI) is
set. This field does not generate an interrupt. * Bit 23 -
1'b1: Error during data transfer by the Tx DMA -
1'b0: Error during data transfer by the Rx DMA * Bit
24 - 1'b1: Error during read transfer - 1'b0: Error
during write transfer * Bit 25 - 1'b1: Error during
descriptor access - 1'b0: Error during data buffer
access
This field indicates the Transmit DMA FSM state.
This field does not generate an interrupt.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Description
Description
No Interrupt
GMAC Line Interrupt
Description
Stopped Reset or Stop Transmit Command
Running: Fetching Tranmit Transfer
Descriptor
Running; Waiting for status
Running; Reading Data host memory buffer
and queuing it to transmit buffer (Tx FIFO)
TIME_STAMP write state
Reserved for future use
Suspended; Transmit Descriptor Unavailable
or Transmit Buffer Underflow
Running; Closing Transmit Descriptor
17-845
Status
Access Reset
RO 0x0
RO 0x0
RO 0x0
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