Altera cyclone V Technical Reference page 2049

cv_5v4
17-834
DMA Register Group Register Descriptions
2016.10.28
Transmit_Poll_Demand
on page 17-839
The Transmit Poll Demand register enables the Tx DMA to check whether or not the DMA owns the
current descriptor. The Transmit Poll Demand command is given to wake up the Tx DMA if it is in the
Suspend mode. The Tx DMA can go into the Suspend mode because of an Underflow error in a
transmitted frame or the unavailability of descriptors owned by it. You can give this command anytime
and the Tx DMA resets this command when it again starts fetching the current descriptor from host
memory.
Receive_Poll_Demand
on page 17-840
The Receive Poll Demand register enables the receive DMA to check for new descriptors. This command is
used to wake up the Rx DMA from the SUSPEND state. The RxDMA can go into the SUSPEND state only
because of the unavailability of descriptors it owns.
Receive_Descriptor_List_Address
on page 17-841
The Receive Descriptor List Address register points to the start of the Receive Descriptor List. The
descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned
(for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by
making the corresponding LS bits low. Writing to this register is permitted only when reception is stopped.
When stopped, this register must be written to before the receive Start command is given. You can write to
this register only when Rx DMA has stopped, that is, Bit 1 (SR) is set to zero in Register 6 (Operation
Mode Register). When stopped, this register can be written with a new descriptor list address. When you
set the SR bit to 1, the DMA takes the newly programmed descriptor base address. If this register is not
changed when the SR bit is set to 0, then the DMA takes the descriptor address where it was stopped
earlier.
Transmit_Descriptor_List_Address
on page 17-842
The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The
descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned
(for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by
making the corresponding LSB to low. You can write to this register only when the Tx DMA has stopped,
that is, Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can
be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly
programmed descriptor base address. If this register is not changed when the ST bit is set to 0, then the
DMA takes the descriptor address where it was stopped earlier.
Status
on page 17-843
The Status register contains all status bits that the DMA reports to the host. The software driver reads this
register during an interrupt service routine or polling. Most of the fields in this register cause the host to
be interrupted. The bits of this register are not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0]
of this register clears these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by
masking the appropriate bit in Register 7 (Interrupt Enable Register).
Operation_Mode on page 17-848
The Operation Mode register establishes the Transmit and Receive operating modes and commands. This
register should be the last CSR to be written as part of the DMA initialization.
Interrupt_Enable on page 17-855
The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to
1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
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