Altera cyclone V Technical Reference page 2065

Hard processor system

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Operation_Mode

Altera Corporation

When this bit is set, transmission starts when a full

frame resides in the MTL Transmit FIFO. When this

bit is set, the TTC values specified in Bits[16:14] are

ignored. This bit should be changed only when the

transmission is stopped.

When this bit is set, the transmit FIFO controller

logic is reset to its default values and thus all data in

the Tx FIFO is lost or flushed. This bit is cleared

internally when the flushing operation is completed.

The Operation Mode register should not be written to

until this bit is cleared. The data which is already

accepted by the MAC transmitter is not flushed. It is

scheduled for transmission and results in underflow

and runt frame transmission. Note: The flush

operation is complete only when the Tx FIFO is

emptied of its contents and all the pending Transmit

Status of the transmitted frames are accepted by the

host. To complete this flush operation, the PHY

transmit clock is required to be active.

Tx Does not Start with Full Frame

Tx Start with Full Frame

Tx FIFO Data not Flushed

TX FIFO Data Flushed

Ethernet Media Access Controller

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