Altera cyclone V Technical Reference page 2064

cv_5v4
2016.10.28
31 30
Reserved
15 14
ttc
RW 0x0
0x0
Operation_Mode Fields
Bit
26
dt
25
rsf
24
dff
Ethernet Media Access Controller
Send Feedback
29 28 27 26
dt
RW
0x0
13 12 11 10
st rfd rfa
RW RW 0x0 RW 0x0
Name
When this bit is set, the MAC does not drop the
frames which only have errors detected by the Receive
Checksum Offload engine. Such frames do not have
any errors (including FCS error) in the Ethernet
frame received by the MAC but have errors only in
the encapsulated payload. When this bit is reset, all
error frames are dropped if the FEF bit is reset.
Value
0x0
0x1
When this bit is set, the MTL reads a frame from the
Rx FIFO only after the complete frame has been
written to it, ignoring the RTC bits. When this bit is
reset, the Rx FIFO operates in the cut-through mode,
subject to the threshold specified by the RTC bits.
Value
0x0
0x1
When this bit is set, the Rx DMA does not flush any
frames because of the unavailability of receive
descriptors or buffers as it does normally when this
bit is reset.
Value
0x0
0x1
Bit Fields
25 24 23 22
rsf dff Reserved
RW RW
0x0 0x0
9 8 7 6
efc fef fuf
RW RW RW
0x0 0x0 0x0
Description
Description
All Error Frames Dropped
MAC does not drop frame with errors
Description
Rx Fifo cut-through mode
Read Rx FIFO only after complete frame
Description
Rx DMA Flushed
Rx DMA not Flushed
Operation_Mode
21 20 19 18
tsf ftf Reserved
RW RW
0x0 0x0
5 4 3 2
Reser rtc osf
ved
RW 0x0 RW
0x0
Access
17-849
17 16
ttc
RW 0x0
1 0
sr Reserved
RW
0x0
Reset
RW 0x0
RW 0x0
RW 0x0
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