ST STM32L4+ Series Reference Manual page 1262

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Advanced-control timers (TIM1/TIM8)

Bits 13:12 ETPS[1:0]: External trigger prescaler

External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A

prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external

00: Prescaler OFF

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

Bits 11:8 ETF[3:0]: External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the

digital filter applied to ETRP. The digital filter is made of an event counter in which N

consecutive events are needed to validate a transition on the output:

0000: No filter, sampling is done at f

Bit 7 MSM: Master/slave mode

0: No action

1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect

synchronization between the current timer and its slaves (through TRGO). It is useful if we

want to synchronize several timers on a single external event.

Bits 6:4 TS[2:0]: Trigger selection

This bit-field selects the trigger input to be used to synchronize the counter.

000: Internal Trigger 0 (ITR0)

001: Internal Trigger 1 (ITR1)

010: Internal Trigger 2 (ITR2)

011: Internal Trigger 3 (ITR3)

100: TI1 Edge Detector (TI1F_ED)

101: Filtered Timer Input 1 (TI1FP1)

110: Filtered Timer Input 2 (TI2FP2)

111: External Trigger input (ETRF)

meaning for each Timer.

Note: These bits must be changed only when they are not used (e.g. when SMS=000) to

Note: The other bit is at position 16 in the same register

Bit 3 Reserved, must be kept at reset value.

Table 275: TIMx internal trigger connection on page 1263

avoid wrong edge detections at the transition.

RM0432 Rev 6

for more details on ITRx

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