Bus Control Register H (Bcrh) - Renesas H8S/2633 Series Hardware Manual

Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of
program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set
to 1.
Bit 3 Bit 2
W11 W10
0 0
1
1 0
1
Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of
program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set
to 1.
Bit 1 Bit 0
W01 W00
0 0
1
1 0
1
7.2.4

Bus Control Register H (BCRH)

7
Bit :
ICIS1
Initial value : 1
R/W : R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 0.
BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Note: * DRAM interface is not available in the H8S/2695.
Only a 0 may be written to RMTS2, RMTS1, or RMTS0.
Description
Program wait not inserted when external space area 1 is accessed
1 program wait state inserted when external space area 1 is accessed
2 program wait states inserted when external space area 1 is accessed
3 program wait states inserted when external space area 1 is accessed
Description
Program wait not inserted when external space area 0 is accessed
1 program wait state inserted when external space area 0 is accessed
2 program wait states inserted when external space area 0 is accessed
3 program wait states inserted when external space area 0 is accessed
6 5
ICIS0 BRSTRM
1 0
R/W R/W
4
3
RMTS2 *
BRSTS1 BRSTS0
1 0
R/W R/W
(Initial value)
(Initial value)
2 1
RMTS1 * RMTS0 *
0 0
R/W R/W R/W
0
0
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