Register Descriptions; Bus Control Register (Bcr) - Renesas H8S/2158 User Manual

Section 6 Bus Controller
6.3

Register Descriptions

The bus controller has the following registers. For details on the system control register, see
section 3.2.2, System Control Register (SYSCR).

• Bus control register (BCR)

• Bus control register 2 (BCR2)
• Wait state control register (WSCR)
• Wait state control register 2 (WSCR2)
6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space or the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit Bit Name Initial Value

7 1
6 ICIS 1
5 BRSTRM 0
Rev. 3.00 Jan 25, 2006 page 106 of 872
REJ09B0286-0300
R/W Description
R/(W) Reserved
The initial value should not be changed.
R/W Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle
cycle between successive external read and
external write cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
R/W Burst ROM Enable
Selects the bus interface for the external address
space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR and the CPCSE
bit in BCR2 are set to 1, burst ROM interface
cannot be selected for the 256-kbyte expansion
area and CP/CF expansion area.