(a) When software STOP mode is canceled by DCNMIm or INTn input
clk
VBCLK (Input)
STPRQ (Output)
STPAK (Input)
SWSTOPRQ (Output)
DCNMIm (Input)
INTn (Input)
CGREL (Input)
Remarks 1. The DCNMIm and INTn inputs are detected at the rising edge and the interrupt request is held in
the CPU.
2. m = 2 to 0, n = 63 to 0
(b) When software STOP mode is canceled by DCRESZ input
clk
VBCLK (Input)
STPRQ (Output)
STPAK (Input)
SWSTOPRQ (Output)
DCRESZ (Input)
CGREL (Input)
Note Input a high level to the DCRESZ pin after restarting input of VBCLK.
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CHAPTER 6 STBC
Figure 6-5. Software STOP Mode Set/Cancel Timing Example
Preliminary User's Manual A14874EJ3V0UM
Oscillation stabilization time
Oscillation stabilization time
1 clock or more
Note
1 clock or more