Figure 6.11 Bus Timing For 16-Bit, 2-State Access Space (Even Address Byte Access) - Renesas H8S/2368 Series Hardware Manual

16-Bit, 2-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Read
Write
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space
Rev. 2.00, 05/03, page 142 of 820
Address bus
D15 to D8
D7 to D0
D15 to D8
D7 to D0
(Even Address Byte Access)
Bus cycle
T T
1 2
High
Valid
High impedance
Valid
Invalid