Figure 6.7 Bus Timing For 16-Bit, 2-State Access Space (Even Byte Access) - Renesas H8S/2437 Hardware Manual

16-Bit, 2-State Access Space:
Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space
is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower
half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Read
Write
Note:

Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)

Address bus
D15 to D8
D7 to D0
D15 to D8
D7 to D0
n = 1 to 3
Bus cycle
T T
1 2
High
Valid
Undefined
Rev. 1.00, 09/03, page 107 of 704
Valid
Invalid