Slave Receive Operation; Figure 13.16 Example Of Stop Condition Issuance Timing In Master Receive Mode (Mls = Ackb = 0, Wait = 1) - Renesas H8S/2111B Hardware Manual

SCL
8
(master output)
SDA
Bit 0
(slave output)
Data 2 [3]
SDA
(master output)
IRIC
IRTR
[4] IRTR=0
ICDR Data 1
User processing
[6] IRIC clear
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
13.4.5

Slave Receive Operation

2
In I C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Receive Operation Using the HNDS Function (HNDS = 1):
Figure 13.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1).
[8] Wait for one clock pulse
9
1 2 3
Bit 7 Bit 6 Bit 5
Data 3
[3]
A
[4] IRTR=1
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
(MLS = ACKB = 0, WAIT = 1)
7
4 5 6 8
Bit 2
Bit 4 Bit 3 Bit 1
Bit 0
Data 2
[14] IRIC clear
Stop condition generation
9
[12]
[12]
A
[13] IRTR=0 [13] IRTR=1
Data 3
[15] WAIT cleared
to 0, IRIC clear
[17] Stop condition
issuance
[16] ICDR read
Rev. 1.00, 05/04, page 321 of 544
(Data 3)