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M16C/29 Group
14.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDA
to low while the SCL
when the SDA
Because the start and stop condition-detected interrupts share the interrupt control register and vec-
tor, check the U2SMR register's BBS bit to determine which interrupt source is requesting the inter-
rupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
SCL2
SDA2
(Start condition)
SDA2
(Stop condition)
Note: When the PCLKR register's PCLK1 bit = "1", this is the cycle number of
f
1SIO
Figure 14.1.3.1.1. Detection of Start and Stop Condition
14.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the U2SMR4 register's STAREQ bit to "1" (start).
A restart condition is generated by setting the U2SMR4 register's RSTAREQ bit to "1" (start).
A stop condition is generated by setting the U2SMR4 register's STPREQ bit to "1" (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to "1" (start).
(2) Set the STSPSEL bit in the U2SMR4 register to "1" (output).
Make sure that no interrupts or DMA transfers will occur between (1) and (2).
The function of the STSPSEL bit is shown in Table 14.1.3.2.1 and Figure 14.1.3.2.1.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
pin is in the high state. A stop condition-detected interrupt request is generated
2
pin changes state from low to high while the SCL
2
; when PCLK1 bit = "0", this is the cycle number of f
page 193 of 402
14.1.3 Special Mode 1 (I
Duration for
Duration for
setting up
2
C bus mode) (UART2)
pin changes state from high
2
pin is in the high state.
2
holding
.
2SIO
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