Signal Description; Memory Map/Register Description - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

• Ability of timers to generate interrupts

• Maskable interrupts

• Independent timeout periods for each timer

40.3 Signal description

The PIT module has no external pins.

This section provides a detailed description of all registers accessible in the PIT module.

• Reserved registers will read as 0, writes will have no effect.

• See the chip-specific PIT information for the number of PIT channels used in this

PIT Module Control Register (PIT_MCR)

Timer Load Value Register (PIT_LDVAL0)

Current Timer Value Register (PIT_CVAL0)

Timer Control Register (PIT_TCTRL0)

4003_710C Timer Flag Register (PIT_TFLG0)

Timer Load Value Register (PIT_LDVAL1)

Current Timer Value Register (PIT_CVAL1)

Timer Control Register (PIT_TCTRL1)

4003_711C Timer Flag Register (PIT_TFLG1)

Timer Load Value Register (PIT_LDVAL2)

Current Timer Value Register (PIT_CVAL2)

Timer Control Register (PIT_TCTRL2)

4003_712C Timer Flag Register (PIT_TFLG2)

Timer Load Value Register (PIT_LDVAL3)

Current Timer Value Register (PIT_CVAL3)

Timer Control Register (PIT_TCTRL3)

4003_713C Timer Flag Register (PIT_TFLG3)

Freescale Semiconductor, Inc.

PIT memory map

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 40 Periodic Interrupt Timer (PIT)