Stop Mode Operation; Background Debug Mode Operation; Start-Up And Operation - NXP Semiconductors freescale KV4 Series Reference Manual

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35.4.2.2 Stop mode operation

Depending on clock restrictions related to the MCU core or core peripherals, the MCU is

brought out of stop when a compare event occurs and the corresponding interrupt is

enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the

normal operating mode and comparator output is placed onto the external pin. In Stop

modes, the comparator can be operational in both:

• High-Speed (HS) Comparison mode when CR1[PMODE] = 1

• Low-Speed (LS) Comparison mode when CR1[PMODE] = 0

It is recommended to use the LS mode to minimize power consumption.

If stop is exited with a reset, all comparator registers are put into their reset state.

When the microcontroller is in active background debug mode, the CMP continues to

operate normally.

35.4.3 Startup and operation

A typical startup sequence is listed here.

• The time required to stabilize COUT will be the power-on delay of the comparators

plus the largest propagation delay from a selected analog source through the analog

comparator, windowing function and filter. See the Data Sheets for power-on delays

of the comparators. The windowing function has a maximum of one bus clock period

delay. The filter delay is specified in the

• During operation, the propagation delay of the selected data paths must always be

considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF]

to reflect an input change or a configuration change to one of the components

involved in the data path.

• When programmed for filtering modes, COUT will initially be equal to 0, until

sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if

COUTA is at a logic 1.

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 35 Comparator (CMP)