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JTAG status and control registers
9.4.1 MDM-AP Control Register
Table 9-4. MDM-AP Control register assignments
Bit
Name
0
Flash Mass Erase in Progress
1
Debug Disable
2
Debug Request
3
System Reset Request
4
Core Hold Reset
5
VLLSx Debug Request
(VLLDBGREQ)
6
VLLSx Debug Acknowledge
(VLLDBGACK)
7
VLLSx Status Acknowledge
1. Command available in secure mode
122
1
Secure
Y
Set to cause mass erase. Cleared by hardware after mass erase
operation completes.
When mass erase is disabled (via MEEN and SEC settings), the erase
request does not occur and the Flash Mass Erase in Progress bit
continues to assert until the next system reset.
N
Set to disable debug. Once it is set, the MDM-AP register cannot be
written and it can only be cleared by debug reset.
N
Set to force the Core to halt.
If the Core is in a stop or wait mode, this bit can be used to wakeup the
core and transition to a halted state.
N
Set to force a system reset. The system remains held in reset until this
bit is cleared.
N
Configuration bit to control Core operation at the end of system reset
sequencing.
0 Normal operation - release the Core from reset along with the rest of
the system at the end of system reset sequencing.
1 Suspend operation - hold the Core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the Core from reset and CPU
operation begins.
N
Set to configure the system to be held in reset after the next recovery
from a VLLSx mode.
This bit holds the in reset when VLLSx modes are exited to allow the
debugger time to re-initialize debug IP before the debug session
continues.
The Mode Controller captures this bit logic on entry to VLLSx modes.
Upon exit from VLLSx modes, the Mode Controller holds the in reset
until VLLDBGACK is asserted.
The VLLDBGREQ bit clears automatically due to the POR reset
generated as part of the VLLSx recovery.
N
Set to release a being held in reset following a VLLSx recovery
This bit is used by the debugger to release the system reset when it is
being held on VLLSx mode exit. The debugger re-initializes all debug
IP and then assert this control bit to allow the Mode Controller to
release the from reset and allow CPU operation to begin.
The VLLDBGACK bit is cleared by the debugger or can be left set
because it clears automatically due to the POR reset generated as part
of the next VLLSx recovery.
N
Set this bit to acknowledge the DAP VLLS Status bit has been read.
This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the stickyVLLSx mode entry
status bits. This bit is asserted and cleared by the debugger.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Description
Freescale Semiconductor, Inc.
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