Table of Contents
Advertisement
Memory map and register definition
11.7.2 Global Pin Control Low Register (PORTx_GPCLR)
Only 32-bit writes are supported to this register.
Address: Base address + 80h offset
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–16
Global Pin Write Enable
GPWE
Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.
0
Corresponding Pin Control Register is not updated with the value in GPWD.
1
Corresponding Pin Control Register is updated with the value in GPWD.
GPWD
Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
11.7.3 Global Pin Control High Register (PORTx_GPCHR)
Only 32-bit writes are supported to this register.
Address: Base address + 84h offset
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–16
Global Pin Write Enable
GPWE
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD.
0
Corresponding Pin Control Register is not updated with the value in GPWD.
1
Corresponding Pin Control Register is updated with the value in GPWD.
GPWD
Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
138
25
24
23
22
21
20
19
18
0
GPWE
0
0
0
0
0
0
0
0
PORTx_GPCLR field descriptions
25
24
23
22
21
20
19
18
0
GPWE
0
0
0
0
0
0
0
0
PORTx_GPCHR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
9
8
7
6
5
4
3
2
0
GPWD
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
0
GPWD
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
1
0
0
0
1
0
0
0
Advertisement
Table of Contents
