Fault Pin Filter; Automatic Fault Clearing - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

37.5.2.12.1 Fault Pin Filter

Each fault pin has a programmable filter that can be bypassed. The sampling period of the

filter can be adjusted with FFILT[FILT_PER]. The number of consecutive samples that

must agree before an input transition is recognized can be adjusted using

FFILT[FILT_CNT]. Setting FFILT[FILT_PER] to all 0 disables the input filter for a

given FAULTx pin.

Upon detecting a logic 0 on the filtered FAULTx pin (or a logic 1 if FCTRL[FLVLx] is

set), the corresponding FSTS[FFPINx] and fault flag, FSTS[FFLAGx], bits are set.

FSTS[FFPINx] remains set as long as the filtered FAULTx pin is zero. Clear

FSTS[FFLAGx] by writing a logic 1 to FSTS[FFLAGx].

If the FIEx, FAULTx pin interrupt enable bit is set, FSTS[FFLAGx] generates a CPU

interrupt request. The interrupt request latch remains set until:

• Software clears FSTS[FFLAGx] by writing a logic one to the bit

• Software clears the FIEx bit by writing a logic zero to it

• A reset occurs

Even with the filter enabled, there is a combinational path from the FAULTx inputs to the

PWM pins. This logic is also capable of holding a fault condition in the event of loss of

clock to the PWM module.

Setting an automatic clearing mode bit, FCTRL[FAUTOx], configures faults from the

FAULTx pin for automatic clearing.

When FCTRL[FAUTOx] is set, disabled PWM pins are enabled when the FAULTx pin

returns to logic one and a new PWM full or half cycle begins. See the following figure. If

FSTS[FFULLx] is set, then the disabled PWM pins are enabled at the start of a full cycle.

If FSTS[FHALFx] is set, then the disabled PWM pins are enabled at the start of a half

cycle. Clearing FSTS[FFLAGx] does not affect disabled PWM pins when

FCTRL[FAUTOx] is set.

Freescale Semiconductor, Inc.

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)

KV4x Reference Manual, Rev. 2, 02/2015