Cmp Status And Control Register (Cmpx_Scr) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definitions

24.3.4 CMP Status and Control Register (CMPx_SCR)

Address: 4007_3000h base + 3h offset = 4007_3003h
Bit 7
Read 0
Write
Reset 0
Field
7 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
6 DMA Enable Control
DMAEN
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is
asserted when CFR or CFF is set.
0 DMA is disabled.
1 DMA is enabled.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 Comparator Interrupt Enable Rising
IER
Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is
set.
0 Interrupt is disabled.
1 Interrupt is enabled.
3 Comparator Interrupt Enable Falling
IEF
Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is
set.
0 Interrupt is disabled.
1 Interrupt is enabled.
2 Analog Comparator Flag Rising
CFR
Detects a rising-edge on COUT, when set, during normal operation. CFR is cleared by writing 1 to it.
During Stop modes, CFR is edge sensitive .
0 Rising-edge on COUT has not been detected.
1 Rising-edge on COUT has occurred.
1 Analog Comparator Flag Falling
CFF
Detects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it.
During Stop modes, CFF is edge sensitive .
0 Falling-edge on COUT has not been detected.
1 Falling-edge on COUT has occurred.
400
6 5
0
DMAEN
0 0
CMPx_SCR field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4 3
CFR
IER IEF
0 0
Description
2 1
CFF COUT
w1c w1c
0 0
Freescale Semiconductor, Inc.
0
0