I2C Smbus Control And Status Register (I2C_Smb) - NXP Semiconductors freescale KV4 Series Reference Manual

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This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address

scheme. If I2C_C2[RMEN] is set to 1, any nonzero value write enables this register. This register value

can be considered as a maximum boundary in the range matching mode.

This field is reserved.

This read-only field is reserved and always has the value 0.

45.4.9 I2C SMBus Control and Status register (I2C_SMB)

When the SCL and SDA signals are held high for a length of

time greater than the high timeout period, the SHTF1 flag sets.

Before reaching this threshold, while the system is detecting

how long these signals are being held high, a master assumes

that the bus is free. However, the SHTF1 bit is set to 1 in the

bus transmission process with the idle bus state.

When the TCKSEL bit is set, there is no need to monitor the

SHTF1 bit because the bus speed is too high to match the

protocol of SMBus.

Address: 4006_6000h base + 8h offset = 4006_6008h

Fast NACK/ACK Enable

For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result

of receiving data byte.

An ACK or NACK is sent on the following receiving data byte

Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a

data byte generates a NACK.

SMBus Alert Response Address Enable

Enables or disables SMBus alert response address matching.

NOTE: After the host responds to a device that used the alert response address, you must use software

to put the device's address on the bus. The alert protocol is described in the SMBus specification.

Freescale Semiconductor, Inc.

I2C_RA field descriptions (continued)

I2C_SMB field descriptions

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KV4x Reference Manual, Rev. 2, 02/2015

Chapter 45 Inter-Integrated Circuit (I2C)