Baud Rate Tolerance; Slow Data Tolerance - NXP Semiconductors freescale KV4 Series Reference Manual

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The following figure shows receiver hardware flow control functional timing. Along with

the actual character itself, RXD shows the start bit. The stop bit can also indicated, with a

dashed line, if necessary. The watermark is set to 2.

Figure 46-74. Receiver hardware flow control timing diagram

46.5.2.8 Baud rate tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud

rate. Accumulated bit time misalignment can cause one of the three stop bit data samples

(RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the

RT8, RT9, and RT10 samples are not all the same logical values. A framing error will

occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9,

and RT10 stop bit samples are a logic 0.

As the receiver samples an incoming frame, it resynchronizes the RT clock on any valid

falling edge within the frame. Resynchronization within frames corrects a misalignment

between transmitter bit times and receiver bit times.

The following figure shows how much a slow received frame can be misaligned without

causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1

but arrives in time for the stop bit data samples at RT8, RT9, and RT10.

Freescale Semiconductor, Inc.

Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI

C1 in reception

KV4x Reference Manual, Rev. 2, 02/2015