Uart Baud Rate Registers: Low (Uartx_Bdl); Uart Control Register 1 (Uartx_C1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

38.4.2 UART Baud Rate Registers: Low (UARTx_BDL)

This register, along with the BDH register, controls the prescale divisor for UART baud

rate generation. To update the 13-bit baud rate setting, SBR[12:0], first write to BDH to

buffer the high half of the new value and then write to BDL. The working value in BDH

does not change until BDL is written. BDL is reset to a nonzero value, but after reset, the

baud rate generator remains disabled until the first time the receiver or transmitter is

enabled, that is, when C2[RE] or C2[TE] is set.

Address: 4006_C000h base + 1h offset = 4006_C001h

UART Baud Rate Bits

The baud rate for the UART is determined by the 13 SBR fields. See

This read/write register controls various optional features of the UART system.

Address: 4006_C000h base + 2h offset = 4006_C002h

Loop Mode Select

When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally

connected to the receiver input. The transmitter and the receiver must be enabled to use the loop function.

Freescale Semiconductor, Inc.

Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)

UARTx_BDL field descriptions

• The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after

reset.The baud rate generator is disabled when SBR = 0.

• Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data

in a temporary location until BDL is written.

UARTx_C1 field descriptions

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Baud rate generation

for details.