Uart Baud Rate Registers: High (Uartx_Bdh) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Memory map and registers

UART 7816 Wait and Guard Parameter Register

(UART2_WGP7816_T1)

UART 7816 Wait Parameter Register C

(UART2_WP7816C_T1)

38.4.1 UART Baud Rate Registers: High (UARTx_BDH)

This register, along with the BDL register, controls the prescale divisor for UART baud

rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to

buffer the high half of the new value and then write to BDL. The working value in BDH

does not change until BDL is written.

BDL is reset to a nonzero value, but after reset, the baud rate generator remains disabled

until the first time the receiver or transmitter is enabled, that is, when C2[RE] or C2[TE]

Address: 4006_C000h base + 0h offset = 4006_C000h

This field is reserved.

RxD Input Active Edge Interrupt Enable

Enables the receive input active edge, RXEDGIF, to generate interrupt requests.

Hardware interrupts from RXEDGIF disabled using polling.

RXEDGIF interrupt request enabled.

This field is reserved.

This read-only field is reserved and always has the value 0.

UART Baud Rate Bits

The baud rate for the UART is determined by the 13 SBR fields. See

UART memory map (continued)

UARTx_BDH field descriptions

• The baud rate generator is disabled until C2[TE] or C2[RE] is set for the first time after

reset.The baud rate generator is disabled when SBR = 0.

• Writing to BDH has no effect without writing to BDL, because writing to BDH puts the data

in a temporary location until BDL is written.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Baud rate generation

for details.

Freescale Semiconductor, Inc.