I2C Range Address Register (I2Cx_Ra); I2C Smbus Control And Status Register (I2Cx_Smb) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Controls the width of the glitch, in terms of I2C module clock cycles, that the filter must absorb. For any

glitch whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.

No filter/bypass

Filter glitches up to width of n I2C module clock cycles, where n=1-15d

36.4.8 I2C Range Address register (I2Cx_RA)

Address: Base address + 7h offset

Range Slave Address

This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address

scheme. If I2C_C2[RMEN] is set to 1, any nonzero value write enables this register. This register value

can be considered as a maximum boundary in the range matching mode.

This field is reserved.

This read-only field is reserved and always has the value 0.

When the SCL and SDA signals are held high for a length of

time greater than the high timeout period, the SHTF1 flag sets.

Before reaching this threshold, while the system is detecting

how long these signals are being held high, a master assumes

that the bus is free. However, the SHTF1 bit is set to 1 in the

bus transmission process with the idle bus state.

When the TCKSEL bit is set, there is no need to monitor the

SHTF1 bit because the bus speed is too high to match the

protocol of SMBus.

Freescale Semiconductor, Inc.

I2Cx_FLT field descriptions (continued)

I2Cx_RA field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 36 Inter-Integrated Circuit (I2C)