Block Diagram; Llwu Signal Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Chapter 19 Low-Leakage Wakeup Unit (LLWU)

19.2.2.1 VLLS modes

All wakeup and reset events result in VLLS exit via a reset flow.

19.2.2.2 Non-low leakage modes

The LLWU is not active in all non-low leakage modes where detection and control logic

are in a static state. The LLWU registers are accessible in non-low leakage modes and are

available for configuring and reading status when bus transactions are possible.

When the wake-up pin filters are enabled, filter operation begins immediately. If a low

leakage mode is entered within five LPO clock cycles of an active edge, the edge event

will be detected by the LLWU.

19.2.2.3 Debug mode

When the chip is in Debug mode and then enters a VLLSx mode, no debug logic works

in the fully-functional low-leakage mode. Upon an exit from the VLLSx mode, the

LLWU becomes inactive.

19.2.3 Block diagram

The following figure is the block diagram for the LLWU module.

The signal properties of LLWU are shown in the table found here.

The external wakeup input pins can be enabled to detect either rising-edge, falling-edge,

or on any change.

Table 19-2. LLWU signal descriptions

Wakeup inputs (n = 0- 31)

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.