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MOD = 0x0005
CnV = 0x0003
channel (n) output
Figure 39-180. Example of the Output Compare mode when the match toggles the
MOD = 0x0005
CnV = 0x0003
channel (n) output
CHnF bit
TOF bit
Figure 39-181. Example of the Output Compare mode when the match clears the
MOD = 0x0005
CnV = 0x0003
channel (n) output
CHnF bit
Figure 39-182. Example of the Output Compare mode when the match sets the channel
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the
CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1, however the
channel (n) output is not modified and controlled by FTM.
39.5.6 Edge-Aligned PWM (EPWM) mode
The Edge-Aligned mode is selected when:
• QUADEN = 0
Freescale Semiconductor, Inc.
channel (n)
counter
overflow
match
CNT
...
1
2
0
previous value
CHnF bit
previous value
TOF bit
channel output
counter
channel (n)
overflow
match
CNT
2
...
0
1
3
previous value
previous value
channel output
counter
channel (n)
match
overflow
CNT
...
0
1
2
3
previous value
previous value
TOF bit
output
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
counter
channel (n)
overflow
match
4
5
1
2
3
0
3
counter
channel (n)
overflow
match
4
5
0
1
2
3
counter
channel (n)
overflow
match
4
5
0
1
2
3
Chapter 39 FlexTimer Module (FTM)
counter
overflow
4
5
1
...
0
counter
overflow
...
4
5
0
1
counter
overflow
4
5
0
1
...
959
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