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Memory Map and Register Definition
29.4.5 Channel (n) Value (TPMx_CnV)
These registers contain the captured TPM counter value for the input modes or the match
value for the output modes.
In input capture mode, any write to a CnV register is ignored.
In compare modes, writing to a CnV register latches the value into a buffer. A CnV
register is updated with the value of its write buffer according to
Additional writes to the CnV write buffer are ignored until the register has been updated.
Address: Base address + 10h offset + (8d × i), where i=0d to 5d
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–16
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
VAL
Channel Value
Captured TPM counter value of the input modes or the match value for the output modes. This field must
be written with single 16-bit or 32-bit access.
29.4.6 Capture and Compare Status (TPMx_STATUS)
The STATUS register contains a copy of the status flag, CnSC[CHnF] for each TPM
channel, as well as SC[TOF], for software convenience.
Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be
checked using only one read of STATUS. All CHnF bits can be cleared by writing all
ones to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. Writing
a 1 to CHF clears it. Writing a 0 to CHF has no effect.
If another event occurs between the flag setting and the write operation, the write
operation has no effect; therefore, CHF remains set indicating another event has occurred.
In this case a CHF interrupt request is not lost due to the clearing sequence for a previous
CHF.
468
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
TPMx_CnV field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
CnV Register Update
9
8
7
6
5
4
3
2
VAL
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
.
1
0
0
0
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