Channel (N) Status And Control (Tpmx_Cnsc) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory Map and Register Definition

29.4.4 Channel (n) Status and Control (TPMx_CnSC)

CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function. When switching from one
channel mode to a different channel mode, the channel must first be disabled and this
must be acknowledged in the TPM counter clock domain.
CPWMS
X
X
0
1
Address: Base address + Ch offset + (8d × i), where i=0d to 5d
Bit 31 30 29
R
W
Reset
0 0 0
466
Table 29-5. Mode, Edge, and Level Selection
MSnB:MSnA ELSnB:ELSnA
00
01
00
01
10
11
10
28 27 26 25
0 0 0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Mode
00 None
00 Software compare
01 Input capture
10
11
01 Output compare
10
11
10 Edge-aligned PWM
X1
10 Output compare
01
10 Center-aligned PWM
01
24 23 22 21
0
0 0 0 0
Configuration
Channel disabled
Pin not used for TPM
Capture on Rising Edge
Only
Capture on Falling
Edge Only
Capture on Rising or
Falling Edge
Toggle Output on
match
Clear Output on match
Set Output on match
High-true pulses (clear
Output on match, set
Output on reload)
Low-true pulses (set
Output on match, clear
Output on reload)
Pulse Output low on
match
Pulse Output high on
match
High-true pulses (clear
Output on match-up,
set Output on match-
down)
Low-true pulses (set
Output on match-up,
clear Output on match-
down)
20 19 18 17
0 0 0 0
Freescale Semiconductor, Inc.
16
0