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Memory map/register definition
Absolute
address
(hex)
4007_C000 LLWU Pin Enable 1 register (LLWU_PE1)
4007_C001 LLWU Pin Enable 2 register (LLWU_PE2)
4007_C002 LLWU Pin Enable 3 register (LLWU_PE3)
4007_C003 LLWU Pin Enable 4 register (LLWU_PE4)
4007_C004 LLWU Module Enable register (LLWU_ME)
4007_C005 LLWU Flag 1 register (LLWU_F1)
4007_C006 LLWU Flag 2 register (LLWU_F2)
4007_C007 LLWU Flag 3 register (LLWU_F3)
4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1)
4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2)
18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)
LLWU_PE1 contains the field to enable and select the edge detect type for the external
wakeup input pins LLWU_P3–LLWU_P0.
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction
Address: 4007_C000h base + 0h offset = 4007_C000h
Bit
7
Read
WUPE3
Write
Reset
0
Field
7–6
Wakeup Pin Enable For LLWU_P3
WUPE3
Enables and configures the edge detection for the wakeup pin.
00
External input pin disabled as wakeup input
01
External input pin enabled with rising edge detection
10
External input pin enabled with falling edge detection
11
External input pin enabled with any change detection
5–4
Wakeup Pin Enable For LLWU_P2
WUPE2
Enables and configures the edge detection for the wakeup pin.
268
LLWU memory map
Register name
NOTE
details for more information.
6
5
WUPE2
0
0
LLWU_PE1 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
8
R/W
8
R/W
4
3
WUPE1
0
0
Description
Section/
Reset value
page
00h
18.4.1/268
00h
18.4.2/269
00h
18.4.3/270
00h
18.4.4/271
00h
18.4.5/272
00h
18.4.6/274
00h
18.4.7/276
R
00h
18.4.8/277
00h
18.4.9/279
00h
18.4.10/280
2
1
WUPE0
0
0
Freescale Semiconductor, Inc.
0
0
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