Pulse-Out Enable Register Implementation - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction

38.1.4 Pulse-Out Enable Register Implementation

The following table shows the comparison of pulse-out enable register at the module and
chip level.
Register
POnEN
38.1.5 Pulse-Out Enable Register Implementation
The PDB0 trigger is connected to ADC0 and PDB1 trigger is connected to ADC1.
It is not recommended to use PDB1 to trigger ADC0 or PDB0 to trigger ADC1. It is also
not recommended to use XBARA to route PDB0 to ADC1 or PDB1 to ADC0.
Each of PDB has 4 pre-triggers which can be used to trigger ADC conversion 4 times in
sequence.
User can use the back to back feature of this chip to configure the two PDBs as a signal
chain. The ADC0 scan complete signal can be used as PDB1's Pre-trigger0 acknowledge
and ADC1 scan complete signal can be used as PDB0's Pre-trigger0 acknowledge. See
Figure 38-1
38.2 Introduction
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing
between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the
CMP block.
866
Table 38-5. PDB pulse-out enable register
Module implementation
7:0 - POEN
31:8 - Reserved
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chip implementation
0 - POEN[0] for CMP0
1 - POEN[1] for CMP1
2 - POEN[2] for CMP2
3 - POEN[3] for CMP3
31:4 - Reserved
Freescale Semiconductor, Inc.