Ewm Counter; Ewm Compare Registers; Ewm Refresh Mechanism - NXP Semiconductors freescale KV4 Series Reference Manual

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You must update the CMPH and CMPL registers prior to

enabling the EWM. After enabling the EWM, the counter resets

to zero, therefore providing a reasonable time after a power-on

reset for the external monitoring circuit to stabilize and ensure

that the EWM_in pin is deasserted.

24.5.3 EWM Counter

It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral

bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock

source should be in the kHz range.

The counter is reset to zero, after a CPU reset, or a EWM refresh cycle. The counter

value is not accessible to the CPU.

The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be

modified until another CPU reset occurs.

The EWM compare registers are used to create a service window, which is used by the

CPU to service/refresh the EWM module.

• If the CPU services the EWM when the counter value lies between CMPL value and

CMPH value, the counter is reset to zero. This is a legal service operation.

• If the CPU executes a EWM service/refresh action outside the legal service window,

EWM_out is asserted.

It is illegal to program CMPL and CMPH with same value. In this case, as soon as

counter reaches (CMPL + 1), EWM_out is asserted.

Other than the initial configuration of the EWM, the CPU can only access the EWM by

the EWM Service Register. The CPU must access the EWM service register with correct

write of unique data within the windowed time frame as determined by the CMPL and

CMPH registers. Therefore, three possible conditions can occur:

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 24 External Watchdog Monitor (EWM)