System Pll Configuration - Freescale Semiconductor MPC8358E Hardware Specificftion

22.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters.
multiplication factor encodings for the system PLL.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600–1400 MHz.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
Table 70. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 71. System PLL VCO Divider
RCWL[SVCOD]
00
01
10
11
NOTE
System PLL
Multiplication Factor
× 16
Reserved
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
× 10
× 11
× 12
× 13
× 14
× 15
VCO Divider
4
8
2
Reserved
Clocking
Table 70 shows the
Table 71.
89