Memory Map And Register Definition - Freescale Semiconductor Symphony DSP56724 Reference Manual

7.3

Memory Map and Register Definition

7.3.1 Memory Map
Table 7-5 shows the CGM memory map.
Address
X: $FFFF_7C(SPENA)
X: $FFFF_7D (PCTL)
X: $FFFF_7E(ASCDR)
1
The default value of PCTL should be 0x2B_60C2 if PINIT = 1 during reset.
7.3.2 Register Summary
23
Name
11
X: R/W
$FFFF_7C
Reset
(SPENA)
R/W
Reset
X: R/W
$FFFF_7D
Reset
(PCTL)
R/W
Reset 0
X: R/W
$FFFF_7E
Reset
(ASCDR)
R/W
Reset
7.3.3 Register Descriptions
7.3.3.1 Shared Peripheral Clock Enable Register (SPENA)
The Shared Peripheral Clock Enable register can enable or disable the clock of some shared peripherals.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 7-5. Block Memory Map
Register
Shared Peripheral Clock Enable
Registers.
PLL Control Registers
ASRC Control Division Registers
Table 7-6. Register Summary
22 21 20 19
10 9 8 7
PLKM R4 R3
0 1 0 1
DF2 DF1 DF0 F7
0 0 0 1
Access Reset Value Section/Page
R/W 0x00_0001
R/W 0x2B_60C2
R/W 0x00_0022
18 17 16
6 5 4
R2 R1 R0
0 1 1
F6 F5 F4
1 0 0
ASDF6 ASDF5 ASDF4 ASDF3 ASDF2 ASDF1 ASDF0
0 1 0
Clock Generation Module (CGM)
7.3.3.1/7-7
1
7.3.3.2/7-8
7.3.3.3/7-11
15 14 13
3 2 1
OD1 OD0 PEN
0 1 PINIT
F3 F2 F1
0 0 1
0 0 1
12
0
ASREN
1
PSTP
0
F0
0
0
7-7