Cpu Clock And Peripheral Function Clock; Cpu Clock And Bclk; F 2 , F 8 , F 32 , F 1Sio , F 2Sio , F 8Sio , F 32Sio , F Ad , F Can0 , F C32 ); Clock Output Function - Renesas M16C/60 Series Hardware Manual

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This document is under development and its contents are subject to change.
M16C/6N5 Group

CPU Clock and Peripheral Function Clock

There are existing two type clocks: The CPU clock to operate the CPU and the peripheral function clocks
to operate the peripheral functions.

(1) CPU Clock and BCLK

These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, ring oscillator clock or
the PLL clock.
If the main clock or ring oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit of
CM0 register and the CM17 to CM16 bits of CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to "0"
and the CM17 to CM16 bits to "00
After reset, the main clock divided by 8 provides the CPU clock.
During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU
clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to "0" (output enabled).
Note that when entering stop mode from high- or middle-speed mode, ring oscillator mode or ring oscillator
low power dissipation mode, or when the CM05 bit of CM0 register is set to "1" (main clock turned off) in
low-speed mode, the CM06 bit of CM0 register is set to "1" (divide-by-8 mode).
(2) Peripheral Function Clock (f
These are operating clocks for the peripheral functions.
Two of these, f (i = 1, 2, 8, 32) and f
i
by dividing them by i. The clock f
clocks can be output from the CLK
The f clock is produced from the main clock, PLL clock or ring oscillator clock, and is used for the A-D
AD
converter.
The f clock is derived from the main clock, PLL clock or ring oscillator clock by dividing them by 1
CAN0
(undivided), 2, 4, 8 or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to "1" (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the f , f , f and f
i iSIO AD
The f clock is derived from the sub clock, and is used for timers A and B. This clock can be used when
C32
the sub clock is activated.
Note: f clock stops at "H" in CAN0 sleep mode.
CAN0

Clock Output Function

During single-chip mode, the f
bits of CM0 register to select.
Rev.1.00 2003.05.30 page 54
" (undivided).
2
, f , f
1 2
are derived from the main clock, PLL clock or ring oscillator clock
iSIO
is used for timers A and B, and f
i
pin.
OUT
clocks are turned off (Note).
CAN0
, f or f clock can be output from the CLK
8 32 C
, f , f , f , f , f
8 32 1SIO 2SIO 8SIO
is used for serial I/O. The f
iSIO
Clock Generation Circuit
, f , f , f )
32SIO AD CAN0 C32
pin. Use the CM01 to CM00
OUT
and f
8 32