Clock Output Disabling Function - Renesas H8S Series Hardware Manual

21.8 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port.
When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is
enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, ø clock output is
disabled and input port mode is set. Table 21-5 shows the state of the ø pin in each processing state.
Table 21-5 ø Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
0 1
— 0
High impedance
High impedance Fixed high
High impedance ø output
High impedance ø output
1
Fixed high
Fixed high
Rev.6.00 Oct.28.2004 page 679 of 1016
REJ09B0138-0600H