Table of Contents
Advertisement
M16C/62P Group (M16C/62P, M16C/62PT)
10.5 System Clock Protection Function
The system clock protection function prohibits the CPU clock from changing clock sources when the main
clock is selected the CPU clock source. This prevents the CPU clock from stopping should the program
crash. This function is available when the main clock is selected as the CPU clock source.
When the PM21 bit in the PM2 register is set to "1" (clock change disabled), the following bits cannot be
written to:
• The CM02 bit, CM05 bit and CM07 bit in the CM0 register
• The CM10 bit and CM11 bit in the CM1 register
• The CM20 bit in the CM2 register
• All bits in the PLC0 register
When using the system clock protection function, set the CM05 bit in the CM0 register to "0" (main clock
oscillation) and CM07 bit to "0" (main clock as BCLK clock source) and follow the procedure below.
(1) Set the PRC1 bit in the PRCR register to "1" (write enable).
(2) Set the PM21 bit in the PM2 register to "1" (protects the clock).
(3) Set the PRC1 bit in the PRCR register to "0" (write disable).
When the PM21 bit is set to "1," do not execute the WAIT instruction.
10.6 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re-
oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt are generated. Which is to be generated can be selected using the CM27 bit in the CM2
register. The oscillation stop detection function can be enabled and disabled by the CM20 bit in the CM2
register. Table 10.8 lists an specification overview of the oscillation stop and re-oscillation detect function.
Table 10.8 Specification Overview of Oscillation Stop and Re-Oscillation Detect Function
Item
Oscillation Stop Detectable Clock and
Frequency Bandwidth
Enabling Condition for Oscillation Stop, Set CM20 bit to "1"(enable)
Re-Oscillation Detection Function
Operation at Oscillation Stop,
Re-Oscillation Detection
R
e
. v
2
3 .
0
S
e
p
0
, 1
2
0
0
4
R
E
J
0
9
B
0
1
8
5
0 -
2
3
0
Z
f(XIN) ≥ 2 MHz
•Reset occurs (when CM27 bit =0)
•Oscillation stop, re-oscillation detection interrupt occurs (when CM27 bit =1)
page 85
f o
3
6
4
10. Clock Generating Circuit
Specification
Advertisement
Table of Contents
