System Clock Output Function; Oscillation Stabilization Time At Power-On - Renesas M32R/ECU Series User Manual

18

18.1.4 System Clock Output Function

A clock whose frequency is twice that of the input clock (i.e., the peripheral clock) can be output from the BCLK
pin. The BCLK pin is shared with port P70. To use this pin to output the peripheral clock, set the P7 Operation
Mode Register (P7MOD) bit 8 to "1".
Configuration of the P7 Operation Mode Register is shown below.
P7 Operation Mode Register (P7MOD)
b8 9 10
P70MD P71MD
P72MD
0 0 0
b Bit Name
8 P70MD
Port P70 operation mode bit
9 P71MD
Port P71 operation mode bit
10 P72MD
Port P72 operation mode bit
11 P73MD
Port P73 operation mode bit
12 P74MD
Port P74 operation mode bit
13 P75MD
Port P75 operation mode bit
14 P76MD
Port P76 operation mode bit
15 P77MD
Port P77 operation mode bit

18.1.5 Oscillation Stabilization Time at Power-On

The oscillator circuit comprised of a ceramic (or crystal) resonator requires a finite time before its oscillation
stabilizes after being powered on. Therefore, there must be a certain amount of oscillation stabilization time that
suits the oscillator circuit used.
Figure 18.1.5 shows an oscillation stabilization time required at power-on.
OSC-VCC
RESET#
XIN
Figure 18.1.5 Oscillation Stabilization Time at Power-On
11 12 13 14
P73MD P74MD P75MD P76MD
0 0 0 0
Oscillation stabilization time
b15
P77MD
0
Function
0:P70
1:BCLK
0:P71
1:WAIT#
0:P72
1:HREQ#
0:P73
1:HACK#
0:P74
1:RTDTXD
0:P75
1:RTDRXD
0:P76
1:RTDACK
0:P77
1:RTDCLK
18-7
OSCILLATOR CIRCUIT
18.1 Oscillator Circuit
<Address: H'0080 0747>
<After reset: H'00>
32180 Group User's Manual (Rev.1.0)
R W
R W
R W
R W
R W
R W
R W
R W
R W