Φ Clock Output Disabling Function - Renesas H8S/2319 series Hardware Manual

Oscillator
RES
STBY
φ φ φ φ Clock Output Disabling Function
19.8
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 19-5 shows the state of the φ pin in each processing state.
Table 19-5 φ φ φ φ Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
Figure 19-3 Hardware Standby Mode Timing
0
—
High impedance
High impedance
High impedance
High impedance
Oscillation
stabilization
time
1
0 1
Fixed high
φ output
Fixed high
φ output
Fixed high
Rev. 5.00, 12/03, page 791 of 1088
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