System Clock Output Disabling Function - Renesas F-ZTAT H8 Series Hardware Manual

Section 21 Power-Down State
21.7

System Clock Output Disabling Function

Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state.
Figure 21.3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 21.4 indicates the state of
the φ pin in various operating states.
MSTCR write cycle
(PSTOP = 1)
T1
φ pin
Figure 21.3 Starting and Stopping of System Clock Output
φ φ φ φ Pin State in Various Operating States
Table 21.4
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
Rev. 7.00 Sep 21, 2005 page 676 of 878
REJ09B0259-0700
T2 T3
High impedance
PSTOP = 0
High impedance
Always high
System clock output
System clock output
MSTCR write cycle
(PSTOP = 0)
T1 T2 T3
PSTOP = 1
High impedance
High impedance
High impedance
High impedance