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M16C/29 Group
14.1.1.3 Continuous receive mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register's TI bit is set to "0"
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do
not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON
register bit 2 and bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
14.1.1.4 Serial data logic switch function (UART2)
When the U2C1 register's U2LCH bit = 1 (reverse), the data written to the U2TB register has its logic
reversed before being transmitted. Similarly, the received data has its logic reversed when read from
the U2RB register. Figure 14.1.1.4.1 shows serial data logic.
(1) When the U2C1 register's U2LCH bit = 0 (no reverse)
Transfer clock
(no reverse)
(2) When the U2C1 register's U2LCH bit = 1 (reverse)
Transfer clock
Note: This applies to the case where the U2C0 register's CKPOL bit = 0
Figure 14.1.1.4.1. Serial data logic switch timing
14.1.1.5 Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0
The multiple pins function is valid only when the internal clock is selected for UART1.
Figure 14.1.1.5.1 Transfer Clock Output From Multiple Pins
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
"H"
"L"
TxD
"H"
2
D0
"L"
"H"
"L"
TxD
"H"
2
D0
(reverse)
"L"
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
Microcomputer
T
D
(P6
)
X
1
7
CLKS
(P6
)
1
4
CLK
(P6
)
1
5
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1 (
transfer clock output from multiple pins).
page 178 of 402
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
IN
CLK
Transfer enabled
Transfer enabled
when the UCON
when the UCON
register's
register's
CLKMD0 bit = 0
CLKMD0 bit = 1
14.1 UARTi (i=0 to 2)
D6
D7
D6
D7
). (See Figure 14.1.1.5.1.)
16
IN
CLK
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