Clock Output Disabling Function; Table 20.4 Φ Pin State In Each Processing State - Renesas H8S Series Hardware Manual

φ φ φ φ Clock Output Disabling Function
20.7
The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for
the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus
cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When
DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 20.4 shows the state of the φ pin in each processing state.
Table 20.4 φ φ φ φ Pin State in Each Processing State
Register Settings
DDR PSTOP
0 X
1 0
1 1
Legend:
X: Don't care
Normal Mode Sleep Mode
High impedance High impedance
φ output φ output
Fixed high Fixed high
Section 20 Power-Down Modes
Software
Standby Mode
High impedance
Fixed high
Fixed high
Rev. 6.00 Mar 15, 2006 page 505 of 570
Hardware
Standby Mode
High impedance
High impedance
High impedance
REJ09B0211-0600