Extra Scl Clock Cycle Output Function - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.13.2

Extra SCL Clock Cycle Output Function

In master mode, the RIIC module has a facility for the output of extra SCL (clock) cycles to release the
SDA line of the slave device from being held at the low level due to the master being out of
synchronization with the slave device.
This function is mainly used in master mode to release the SDA line of the slave device from the state
of being fixed to the low level by including extra cycles of SCL output from the RIIC with single
cycles of the SCL (clock) signal as the unit in the case of a bus error where the RIIC cannot issue a stop
condition because the slave device is holding the SDA line at the low level. Do not use this facility in
normal situations. Using it when communications are proceeding correctly will lead to malfunctions.
When the RIICnCR1.CLO bit is set to 1 in master mode, a single cycle of the SCL clock at the
frequency corresponding to the transfer rate settings (settings of the RIICnMR1.CKS[2:0] bits, and of
the RIICnBRH and RIICnBRL registers) is output as an extra clock cycle. After output of this single
cycle of the SCL clock, the CLO bit is automatically cleared to 0. In this case, if the BBSY flag is set to
1, the SCL pin continues outputting the low level. If the BBSY flag is set to 0, the SCL pin goes high.
In addition, further extra clock cycles can be output consecutively by the software program writing 1 to
the CLO bit after having read CLO = 0.
When the RIIC module is in master mode and the slave device is holding the SDA line at the low level
because synchronization with the slave device has been lost due to the effects of noise, etc., the output
of a stop condition is not possible. The facility for output of an extra cycle of the SCL (clock) signal
can be used to output extra cycles of SCL one by one to make the slave device release the SDA line
from being held at the low level, thus recovering the bus from an unusable state. Release of the SDA
line by the slave device can be monitored by reading the RIICnCR1.SDAI bit. After confirming release
of the SDA line by the slave device, complete communications by reissuing the stop condition.
[Output conditions for using the RIICnCR1.CLO bit]
• When the bus is free (RIICnCR2.BBSY flag = 0) or in master mode (RIICnCR2.MST bit = 1 and
BBSY flag = 1)
• When the communication device does not hold the SCL line low
Figure 18.40 shows the operation timing of the extra SCL clock cycle output function (CLO bit).
SCLn
SDAn
IICφ
BBSY
MST
TRS
CLO
Figure 18.40
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
SDAn line is held low due to irregular bits
RIICnBRH RIICnBRL
9
ACK or Data "0"
Accept CLO output
Extra SCL Clock Cycle Output Function (CLO Bit)
RIICnBRH RIICnBRL
Extra clock cycle
output
MSB or Next Data
Write 1 to CLO Write 1 to CLO
18. I²C Bus Interface
RIICnBRH RIICnBRL
Extra clock cycle
output
Data "1"
18-86