Table 5.5 Setting And Clearing Module Standby Mode By Clock Stop Register - Renesas H8/3847R Series Hardware Manual

Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Register
Register Name Bit Name
CKSTPR1 TACKSTP
TCCKSTP
TFCKSTP
TGCKSTP
ADCKSTP
S1CKSTP
S32CKSTP
S31CKSTP
CKSTPR2 LDCKSTP
PWCKSTP
WDCKSTP
AECKSTP
Note: For details of module operation, see the sections on the individual modules.
Operation
1 Timer A module standby mode is cleared
0 Timer A is set to module standby mode
1 Timer C module standby mode is cleared
0 Timer C is set to module standby mode
1 Timer F module standby mode is cleared
0 Timer F is set to module standby mode
1 Timer G module standby mode is cleared
0 Timer G is set to module standby mode
1 A/D converter module standby mode is cleared
0 A/D converter is set to module standby mode
1 SCI1 module standby mode is cleared
0 SCI1 is set to module standby mode
1 SCI3-2 module standby mode is cleared
0 SCI3-2 is set to module standby mode
1 SCI3-1 module standby mode is cleared
0 SCI3-1 is set to module standby mode
1 LCD module standby mode is cleared
0 LCD is set to module standby mode
1 PWM module standby mode is cleared
0 PWM is set to module standby mode
1 Watchdog timer module standby mode is cleared
0 Watchdog timer is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
0 Asynchronous event counter is set to module standby mode
Section 5 Power-Down Modes
Rev. 6.00 Aug 04, 2006 page 153 of 680
REJ09B0145-0600