Module Standby Control Register (Mstcr) - Renesas F-ZTAT H8 Series Hardware Manual

21.2.2

Module Standby Control Register (MSTCR)

MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, DMAC, refresh
controller, and A/D converter modules.
Bit 7
PSTOP
Initial value 0
Read/Write R/W
ø clock stop
Enables or disables
output of the system clock
MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ φ φ φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 1: PSTOP Description
0 System clock output is enabled
1 System clock output is disabled
Bit 6—Reserved: Read-only bit, always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5: MSTOP5 Description
0 ITU operates normally
1 ITU is in standby state
6 5
— MSTOP5 MSTOP4
1 0
— R/W R/W
Reserved bit
Section 21 Power-Down State
4 3 2
MSTOP3 MSTOP2
0 0 0
R/W R/W
Module standby 5 to 0
These bits select modules
to be placed in standby
Rev. 7.00 Sep 21, 2005 page 667 of 878
1 0
MSTOP1 MSTOP0
0 0
R/W R/W
(Initial value)
(Initial value)
REJ09B0259-0700