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Section 26 Power-Down Modes
26.1.1
Standby Control Register (SBYCR)
SBYCR controls power-down modes.
Bit
Bit Name
7
SSBY
6
STS2
5
STS1
4
STS0
3
Rev. 1.00 Apr. 28, 2008 Page 842 of 994
REJ09B0452-0100
Initial
Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-
speed mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode or watch mode
Note that the SSBY bit is not changed even if a mode
transition is made by an interrupt.
Standby Timer Select 2 to 0
On canceling software standby mode or watch mode,
these bits select the wait time for clock stabilization
from clock oscillation start. Select a wait time of 8 ms
(oscillation stabilization time) or more, depending on
the operating frequency. Table 26.2 shows the
relationship between the STS2 to STS0 values and
wait time.
With an external clock, an arbitrary wait time can be
selected. For normal cases, the minimum value is
recommended.
Reserved
The initial value should not be changed.
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